1. Field of the Invention
This invention relates to an artificial sync signal adding circuit, and more particularly to improvements in a circuit in an apparatus for treating an information signal as an imput signal by synchronizing it with a synchronizing signal having a continuous constant period which is involved in the imformation signal, which circuit is capable of carrying out smooth synchronizing operation by generating artificial synchronizing signal and adding it to the input signal when the synchronizing signal is lacking in the input signal.
2. Description of the Prior Art
To treat an information, it is generally required to synchronize the information with an apparatus for treating the information. In this connection, synchronizing signal is adopted. Particularly, in order to synchronize an information signal including a continuous synchronizing signal having a constant period with the treating apparatus, a circuit as shown in FIG. 1 has been proposed.
In FIG. 1, the block A is a PLL circuit while the block B is a sync signal discriminating circuit for discriminating a continuous synchronizing signal having a constant period among the input information signal.
In FIG. 1, the reference numeral 1 designates a phase comparator, 2 a low pass filter, 3 a voltage control oscillator, 4 a frequency divider, 5 a NAND gate, 6 a flip-flop circuit, 7 an AND gate and 8 a counter, respectively.
The phase comparator 1 of the block A compares an output signal of the block B with an output signal of the frequency divider 4 and thereafter puts out the phase difference between those outputs to the low pass filter 2. The input signal is taken off unnecessary components such as frequency component, etc. by the low pass filter 2 and is consequently put out as being control voltage of the voltage control oscillator 3. The output signal from the voltage control oscillator 3 is applied to one of input terminals of the AND gate 7 of the block B as well as to the frequency divider 4 of the block A. The frequency divider 4 divides the oscillating frequency of the input signal by an integer to apply one of the divisions to one of input terminals of the phase comparator 1. If the phase difference between said two input signals is going to increase, the output signal from the low pass filter 2 controls the oscillating frequency of the voltage control oscillator 3 so as to reduce the phase difference. Therefore, the output terminal O of the voltage control oscillator 3 puts out a signal which synchronizes with the phase of a reference input signal applied to the input terminal of the phase comparator 1 of the block A from the block B and has a frequency as being an integral multiple of the frequency of the reference input signal.
In the block B, when the flip-flop circuit 6 is in the condition with the output Q being at a low level and with the output Q being at a high level and the high level signal is applied to the input terminal T, the input terminal S of the flip-flop circuit 6 is triggered through the NAND gate 5 so that the outputs Q and Q put out outputs of a high level and a low level, respectively. Consequently, the counter 8 begins counting of the output signals from the voltage control oscillator 3 of the block A and the output of the NAND gate 5 becomes high irrespective of the input signal T. When the counter 8 counts up a predetermined value, the output terminal W thereof puts out a signal by which the clear terminal U of the counter 8 as well as the input terminal R of the flip-flop circuit 6 recovers in the original condition and the condition of the NAND gate 5 for cutting off the input signal is released. Therefore, by setting the full-counting value of the counter 8 shorter than the period of the synchronizing signal included in the input signal, it can be understood that the output signal of the block B has been obtained as a result of the discrimination of the synchronizing signal.
As described above in FIG. 1, the block A operates as a PLL circuit while the block B descriminates only the continuous synchronizing signal having a constant period among the information signal and applies the synchronizing signal to the block A as a reference signal. Then, at the output terminal O of the block A there can be obtained a signal which synchronizes with the phase of the synchronizing signal and has a frequency of an integral multiple of the synchronizing signal. The interrelation of respective operations of the above-described circuit is shown in FIG. 2.
Thus, the circuit for synchronizing with the information signal including the continuous synchronizing signal having a constant period has certainly been developed. However, in such a circuit, when occurs that a synchronizing signal is missing from the information signal in the course of transmission, alternatively when noises occur after the signal, the input terminal S of the flip-flop circuit 6 of the block B in FIG. 1 is not triggered while it is thereafter triggered by the information signal in the input signal or noises. Therefore, the signal which then appears at the output Q of the flip-flop circuit 6 is not a one obtained as a result of the discrimination. In this case, there are such drawbacks that a lot of time is required since the above condition until the syncronizing signal is again discriminated and that operations of treating an information, etc, is not performed during that time.